In order to follow the Moore's law, the feature sizes of semiconductor devices (for example, field-effect transistors) have been continuously shrinking. The switching characteristic of the transistors may become worse because of the short-channel effects and leakage current problem of a channel under the shrunk feature size. Therefore, improving the performance of the conventional field-effect transistors by shrinking their physical sizes has encountered some difficulties.
Nanowire field-effect transistors (NWFETs) have been developed by existing technologies. FIG. 1 illustrates an existing NWFET. The NWFET includes a silicon substrate 10, and an oxide buried layer 11 on the silicon substrate 10. The NWFET also includes a plurality of convex structures on the oxide buried layer 11. Further, the NWFET includes a first pad region 12 and a second pad region 13 on the convex structures. Further, the NWFET also includes a plurality of nanowires 14 suspending between the first pad region 12 and the second pad region 13. The first pad region 12 and the second pad region 13 are used for subsequently forming a source region and a drain region. The nanowires 14 are used as channel regions. A surrounding gate structure (not shown) may be formed to cover the nanowires 14.
The nanowires 14 are used as channel regions in the NWFET, carriers in the nanowire channels may be away from surfaces of the nanowires 14 because of the quantum confinement effect, thus carrier transportations in the nanowire channels may be less affected by a surface scattering and a lateral electric field. Therefore, a relatively high carrier mobility may be obtained. Further, because the NWFET may have a relatively small channel, and a surrounding gate structure may be used as a gate structure, the modulating ability of the gate structure may be enhanced, and the threshold characteristics may be improved. Therefore, the short-channel effects may be effectively restrained, and the size of a field-effect transistor may be further shrunk. Further, because the surrounding gate structure of a NWFET may enhance the modulating ability of the gate structure of the NWFET, the requirement for thinning the gate dielectric layer may be alleviated.
However, how to optimize the performance of a NWFET is still one of urgent tasks for those skilled in the art. The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.